Semiconductor memory device and method of manufacturing the same

ABSTRACT

A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor memory deviceand a method of manufacturing the same and, more particularly, to asemiconductor memory device of a so-called FLOTOX (Floating Gate TunnelOxide) type having a structure in which a tunnel region having a thininsulating film is locally formed between the drain and floating gate ofa memory transistor and a method of manufacturing the same.

[0003] 2. Description of the Related Art

[0004] In a semiconductor memory device, e.g., an E²PROM, an insulatingfilm consisting of a silicon oxide film is formed on a surface of asilicon semiconductor substrate, and a thin film portion is locallyformed as a tunnel oxide film on the insulating film. A floating gate isformed on this thin tunnel oxide film. In addition, a control gate isformed on the floating gate through a silicon oxide film serving as aninsulating film.

[0005] In a semiconductor memory device arranged into such a FLOTOX typedevice, demands have arisen for an improvement in endurance (the numberof times of writing and erasing) characteristics and in breakdowncharacteristics of a tunnel insulating film. For example, U.S. Pat. No.4,490,900 discloses a means to improve such characteristics, i.e.,discloses a technique of forming a three-layer structure consisting of atunnel oxide film, a nitride oxide film, and an oxide film.

[0006] After experiments with an FLOTOX type E²PROM having theabove-described structure and examination of the results, the presentinventors obtained the following conclusion. A tunnel oxide filmgenerally has a thickness as small as 50 to 150 Å. For this reason, ifthe concentration of an impurity, e.g., phosphorus, of a floating gateon the tunnel oxide film is excessively high, phosphorus is introducedinto the tunnel insulating film. It was found, therefore, that thewithstand voltage of the tunnel insulating film with respect to electroninjection was lowered, and the number of times of rewriting was reduceddue to breakdown of the tunnel insulating film. In addition, variationsin rewriting amount occurred.

[0007] In contrast to this, if the concentration of phosphorus of thefloating gate is decreased, introduction of the impurity into the tunnelinsulating film is suppressed, and the above problem may be solved.However, in the above-described conventional technique, the impurityconcentration of the floating gate is not designed to be low, but is setto be high instead cue to the following reasons.

[0008] In E²PROMs, a polyoxide film obtained by oxidizing a floatinggate is generally used as an insulating film between the floating gateand a control gate. If the phosphorus concentration of the floating gateis low when it is oxidized, the asperity of a surface of the floatinggate upon oxidation is increased. In addition, a polyoxide film at anedge portion of the floating gate is made thinner, and the edge portionis made further acute, thereby decreasing a withstand voltage betweenthe floating gate and the control gate. The edge portion is especiallysusceptible to such influences, and hence a high voltage for rewritingthe E²PROM cannot be applied.

[0009] In addition, if an oxidation temperature for forming a polyoxidefilm on the floating gate is increased, the withstand voltage tends tobe increased. However, redistribution of an impurity of the tunnelinsulating film in a transistor region occurs, and a problem is posed interms of a high packing density for microfabrication.

SUMMARY OF THE INVENTION

[0010] It is an object of the present invention to provide asemiconductor memory device which can reliably suppress degradation inendurance characteristics, breakdown characteristics of a tunnelinsulating film, and the like due to introduction of an impurity intothe tunnel insulating film, and a method of manufacturing the same.

[0011] It is another object to provide a semiconductor memory device inwhich the withstand voltage of an oxide film between a floating gate anda control gate is increased without causing redistribution of animpurity in a tunnel insulating film.

[0012] It is still another object of the present invention to provide amethod of manufacturing a semiconductor memory device wherein animpurity concentration of a floating gate formed in contact with atunnel insulating film can be locally decreased.

[0013] According to a semiconductor memory device of the presentinvention wherein a tunnel insulating film obtained by setting thethickness of a portion of an insulating film to be small is arrangedbetween a drain and a floating gate of a memory transistor, the impurityconcentration of a portion of the floating gate, which is in contactwith the tunnel insulating film, is set to be low, and the impurityconcentration of portions other than the portion in contact with thetunnel insulating film is set to be higher than that of thelow-concentration portion.

[0014] Such a semiconductor memory device is manufactured in thefollowing manner. The manufacturing method comprises the steps offorming a first insulating film on a semiconductor substrate at aposition corresponding to a tunnel region, forming a second insulatingfilm having a thickness larger than that of the first insulating film soas to be in contact therewith, forming a floating gate in which aportion in contact with the first insulating film has a low impurityconcentration, and an impurity concentration of other portions is set tobe higher than that of the portion in contact with the first insulatingfilm, and forming a control gate on the floating gate through a thirdinsulating film.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIGS. 1A to 1F are sectional views, showing a structure of asemiconductor memory device according to an embodiment of the presentinvention, for sequentially explaining the steps in manufacturing thesame;

[0016]FIG. 2 is an equivalent circuit diagram of the semiconductormemory device manufactured in the embodiment shown in FIGS. 1A to 1F;

[0017]FIG. 3 is a graph showing a relationship between the oxidationtemperature and breakdown voltage in the manufacturing steps in FIGS. 1Ato 1F;

[0018]FIG. 4 is a graph showing a relationship between the phosphorusconcentration and breakdown voltage;

[0019]FIG. 5 is a graph showing a relationship between the-nitridingtime and mobility;

[0020]FIG. 6 is a view, showing an arrangement of a chamber, forexplaining a means for forming an insulating film in the manufacturingsteps in FIGS. 1A to 1F;

[0021]FIG. 7 is a flow chart for explaining the steps in forming theinsulating film;

[0022]FIG. 8 is a graph showing the temperature and pressure in thechamber as a function of time;

[0023]FIG. 9 is a band diagram showing a memory element of amanufactured E²PROM;

[0024]FIG. 10 is a graph showing results obtained by experiments with atrap amount of electrons;

[0025]FIG. 11 is a graph showing a comparison between the endurancecharacteristics of a semiconductor memory device manufactured accordingto the steps in FIGS. 1A to 1F and those of a conventional device;

[0026]FIGS. 12A to 12C are graphs respectively showing relationshipsbetween the sputtering time and nitrogen concentration;

[0027]FIG. 13 is a graph for explaining conditions of the nitridingtemperature and the rapid nitriding time, which are used to obtain agood three-layer structure;

[0028]FIGS. 14A and 14B are sectional views showing a structure of asemiconductor memory device according to a second embodiment of thepresent invention in the order of manufacturing steps;

[0029] FIGS. 15 to 17 are sectional views for respectively explainingthird to fifth embodiments of the present invention;

[0030]FIGS. 18A to 18D are sectional views sequentially showing themanufacturing steps according to a sixth embodiment;

[0031]FIGS. 19A and 19B are sectional views for explaining a seventhembodiment of the present invention;

[0032] FIGS. 20 is a sectional view showing a structure of asemiconductor memory device according to an eight embodiment; and

[0033]FIGS. 21A to 21J are sectional views, showing a structure of thememory device in FIG. 20, for sequentially explaining the steps inmanufacturing the same.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] In this embodiment, an FLOTOX type semiconductor memory devicewill be described in accordance with its manufacturing steps. As shownin FIG. 1A, an element region is formed by field oxide films 12 on themajor surface of a semiconductor substrate 11 consisting of a p-typesilicon single crystal. An n⁺-type diffusion region 13 serving as thedrain of a memory transistor is formed in this element region. After athermal oxide film having a thickness of 50 to 150 Å is formed on thesurface of the substrate 11, the resultant structure is subjected to anitriding treatment by lamp heating in an atmosphere of NH₃ to form aninsulating film 14 having a three layer structure constituted by anitride oxide film and an oxide film.

[0035] After the insulating film 14 is formed in this manner, a firstpolysilicon film 15 of a thickness of 200 to 4,000 Å is formed on theinsulating film 14, as shown in FIG. 1B. An insulating film 16consisting of Si₃N₄ is deposited on the first polysilicon film 15 to athickness of 200 to 1,000 Å by LPCVD (Low-Pressure Chemical VaporDeposition). Thereafter, the insulating film 16 and the firstpolysilicon film 15 are etched by normal photolithography or etching,e.g., dry etching so as to leave only a region serving as a prospectivetunnel region in correspondence with the drain region. Subsequently, thenitride oxide film 14 is removed by using a hydrofluoric acid wetetchant to expose the surface of the semiconductor substrate 11.

[0036] As shown in FIG. 1C, a thermal oxide film (SiO₃) 17 having athickness of, e.g., 300 to 700 Å is formed on the resultant structure byusing the insulating film 16 as a mask. After the thermal oxide film 17is formed in this manner, the insulating film 16 above the tunnel regionis removed by using hot phosphoric acid, as shown in FIG. 1D, thusexposing the first polysilicon film 15.

[0037] Subsequently, as shown in FIG. 1E, a second polysilicon film 18containing an impurity (e.g., phosphorus and arsenic) at a highconcentration is deposited on the resultant structure to a thickness of1,000 to 4,000 Å so as to be electrically connected to the firstpolysilicon film 15 on the surface of the semiconductor substrate 11.Thereafter, the second polysilicon film 18 is oxidized to form aninsulating film 19. A third polysilicon film 20 is formed on theinsulating film 19 by the same process as that for the secondpolysilicon film 18.

[0038] When the first to third polysilicon films 15, 18, and 20 areformed in this manner, the first to third polysilicon films 15, 18, and20 and the insulating film 19 are selectively removed to form a floatinggate 181 consisting of the second polysilicon film 18, which willconstitute a memory transistor A together with the first polysiliconfilm 15. A control gate 201 is then formed by the third polysilicon film20, and an insulating film 191 is formed between the floating gate 181and the control gate 201. In correspondence with a selection transistorB region, a gate electrode 182 of the selection transistor B is formedby the second polysilicon film 18.

[0039] When the floating gate 181, the control gate 201, and the gate182 of the selection transistor are formed in this manner, ions areimplanted into the semiconductor substrate 11 to form an n⁺-type sourceregion 21 of the memory transistor A, and an n⁻-type source region 22and a drain region 23 of the selection transistor B.

[0040]FIG. 2 shows an equivalent circuit of an E²PROM having theabove-described arrangement.

[0041] According to the E²PROM having such a structure, since theimpurity concentration of the first polysilicon film 15 formed incontact with the insulating film 14 serving as a tunnel insulating filmis set to be low, introduction of the impurity into the insulating film14 is suppressed. Therefore, the endurance characteristics and thebreakdown characteristics of the tunnel insulating film can be improved.

[0042] Since the impurity concentration of the second polysilicon film18 constituting the floating gate 181 together with the firstpolysilicon film 15 is set to be high, the surface of the floating gate181 is made relatively smooth. In addition, a polyoxide film (not shown)can be formed on an edge portion of the floating gate 181 in anexcellent state. As a result, the floating gate 181 can be formed bythermal oxidation, and hence the withstand voltage of the insulatingfilm 19 can be increased.

[0043] Note that if a portion of the floating gate 181 in contact withthe insulating film 19 formed by thermal oxidation upon formation of thesecond polysilicon film 18 contains an impurity at a whichconcentration, the withstand voltage can be increased in the same manneras described above.

[0044] In this E²PROM, the high impurity concentration range of thefloating gate 181 is determined in association with the formationprocess of the insulating film 19 described with reference to FIG. 1E.If the oxidation temperature is set to be, e.g., 950 to 1,050° C. inconsideration of redistribution of the impurity, the impurityconcentration is preferably set to be about 4.1×10²⁰cm⁻³ or more.

[0045]FIG. 3 shows a relationship between an oxidation temperature T anda breakdown voltage V of the insulating film 19 when a positivepotential is applied to the control gate 201 consisting of the thirdpolysilicon film in the E²PROM having the arrangement shown in FIG. 1F.Referring to FIG. 3, triangle plots represent the characteristics of asample obtained by setting the phosphorus concentration of the floatinggate 181 to be 2.2×10²⁰cm⁻³, whereas circle plots represent thecharacteristics of a sample obtained by setting the phosphorusconcentration to be 4.1×10²⁰cm⁻³. In this case, a precipitationtemperature of polysilicon is 610° C., and a withstand voltagedetermination current value is 4×10⁶ A/mm². Generally, a breakdownvoltage is set to be 4 MV/cm or more in consideration of rewritingcharacteristics. The concentration value of 4.1×10²⁰cm⁻³ is set on thebasis of this breakdown voltage as are reference.

[0046]FIG. 4 shows a relationship between a phosphorus concentration Cpand a breakdown voltage V of the floating gate 181 constituted by thesecond polysilicon film when the insulating film 19 is formed byperforming thermal oxidation in an atmosphere of dry O₂ at 1,000° C. Itis understood from this graph that the breakdown voltage V is increasedwith an increase in phosphorus concentration.

[0047] Note that if the oxidation temperature for the insulating film 19falls outside the range of 950 to 1,050° C., an impurity concentrationin the floating gate 181 constituted by the second polysilicon film isset on the basis of FIGS. 3 and 4.

[0048] In addition, as long as the low impurity concentration range ofthe first polysilicon film 15 is set below the impurity concentration ofthe second polysilicon film 18 constituting the floating gate 181 set inthe above-described manner, a certain effect can be expected. However,the impurity concentration of the floating gate 181 is preferably set tobe as low as possible.

[0049] Furthermore, in the above-described E²PROM, a tunnel oxide filmis constituted by the insulating film 14 constituting a three-layerstructure together with a nitride oxide film and an oxide film, asdisclosed, e.g., in U.S. Pat. No. 4,490,900. Therefore, electrons movingbetween the n⁺-type diffusion region 13 and the first polysilicon film15 through the tunnel insulating film are not easily trapped, and theendurance characteristics and the breakdown characteristics of theE²PROM are further improved.

[0050] According to the manufacturing method disclosed in U.S. Pat. No.4,490,900, when an oxide film serving as a tunnel insulating film is tobe nitrided, a portion near a memory transistor, e.g., a gate oxide filmof a selection transistor is simultaneously nitrided with the tunnelinsulating film. As a result, the mobility of carriers is decreased dueto Coulomb scattering which is considered to be caused by stationarycharge introduced in the gate oxide film upon this nitriding, therebyposing a problem of decreasing the device speed.

[0051]FIG. 5 shows a relationship between a nitriding time (RTN) and amobility PFE when a 430-Å thick gate oxide film is nitrided in anatmosphere of NH₃ at 1,150° C. by using a halogen lamp. As is apparentfrom FIG. 5, the mobility is decreased as the nitriding time isprolonged.

[0052] According to the E²PROM disclosed in this embodiment, a thermaloxide film is nitrided to form the insulating film 14 having athree-layer structure, and the insulating film is then locally removedto form a tunnel insulating film. Therefore, the thermal oxide film 17is not nitrided, and the above-described problem is not posed.

[0053] In this embodiment, the impurity concentration of the firstpolysilicon film 15 in contact with the insulating film 14 serving as atunnel insulating film is decreased by the above-described method. Inaddition to this method, for example, a first polysilicon film 15containing no impurity is formed, and an impurity is then diffusedtherein by ion implantation or by using a gaseous impurity source.

[0054] In this case, the insulating film 14 has a three-layer structureso that excellent endurance characteristics can be obtained withoutmaking the tunnel insulating film especially thin. A method ofmanufacturing this insulating film will be described below. As shown inFIG. 6, a silicon semiconductor wafer 32 is inserted in a quartz chamber31. Gas inlet ports 33 and 34 are formed in the chamber 31. N₂ isintroduced through the inlet port 33, whereas reactive gases such asNH₂, O₂, H₂, and Cl are selectively introduced through the inlet port34. In addition, an exhaust port 35 is formed in the chamber 31, so thatthe chamber 31 is selectively evacuated by a vacuum pump (not shown)through the exhaust port 35.

[0055] Since a heating mechanism constituted by halogen lamps 36 isarranged around the quartz chamber 31, the semiconductor wafer 32 israpidly heated by the halogen lamps 36.

[0056] Note that the heating temperature in the quartz chamber 31 ismonitored so that the halogen lamps 36 are controlled to set the heatingtemperature to a target value, although a detail of such a mechanism isnot shown in FIG. 6. In addition, arc lamps may be used in place of thehalogen lamps.

[0057]FIG. 7 is a flow chart of a process for forming a tunnel oxidefilm in a state wherein the semiconductor wafer 32 is set in the quartzchamber 31. The flow advances to step 101 while the wafer is set in thechamber. In this step, the chamber 31 is evacuated. When the chamber 31is evacuated to a vacuum state, a reactive gas such as H₂ or HCl isintroduced into the chamber as shown in step 102, and the flow thenadvances to step 103 of raising the temperature of the chamber.

[0058] In this third step, a natural oxide film which is inferior inquality formed on a surface of the semiconductor wafer 32 due to air orby a chemical treatment is removed. For example, in step 103, the wafer32 is treated at 1,150° C. for 60 seconds. After the removal treatmentof such a natural oxide film, the temperature of the chamber 31 islowered in the fourth step, i.e., step 104.

[0059] When the temperature of the chamber 31 is lowered in step 104,the chamber 31 is evacuated in the fifth step, i.e., step 105. O₂ isthen introduced in the chamber 31 in the sixth step, i.e., step 106.

[0060] When the semiconductor wafer 32 in the chamber 31 is set in anoxygen atmosphere in this step, the temperature of the wafer 32 in thechamber 31 is raised in the seventh step, i.e., step 107 so as torapidly oxidize the surface of the wafer 32, thus forming a siliconoxide film on the surface of the wafer 32. The temperature raisingtreatment in this step is performed by using the halogen lamps 36 so asto perform especially rapid temperature raise. The silicon oxide film isformed by rapidly oxidizing the surface of the wafer 32.

[0061] The temperature raise/oxidation treatment in the seventh step isperformed at 1,150° C. so as to form a silicon oxide film having athickness of 70 to 90 Å.

[0062] When the silicon oxide film is formed on the surface of thesemiconductor wafer 32 in this manner, the temperature of the wafer 32is lowered in the eight step, i.e., step 108. In addition, the chamber31 is evacuated in the ninth step, i.e., step 109.

[0063] A nitriding reactive gas NH₃ is introduced in the chamber 31 inthe 10th step, i.e., step 110. When such a nitriding reactive gas isintroduced, the semiconductor wafer 32 is rapidly heated by the rapidlyheating means using the halogen lamps 36 in the 11th step, i.e., step111 so as to rapidly nitride the silicon oxide film. This nitriding stepis performed by a heating treatment at 1,1500° C. for 10 seconds.

[0064] When the nitriding treatment is performed in this manner, thetemperature of the chamber 31 is lowered in the 12th step, i.e., step112. In addition, the chamber 31 is evacuated to about 10⁻³ Torr toseveral tens of Torr or an inert gas such as nitrogen is introduced inthe 13th step, i.e., step 113. In the 14th step, i.e., step 114, thesemiconductor wafer 32 is rapidly heated up to 900 to 1,200° C. within30 to 300 seconds by the rapidly heating means constituted by thehalogen lamps 36, thereby performing a stabilization treatment.Thereafter, the temperature of the chamber 31 is lowered in the 15thstep, i.e., step 115. Nitrogen is then introduced in the chamber 31 inthe 16th step, i.e., step 116, and the wafer 32 is taken out from thechamber 31.

[0065]FIG. 8 shows states of- temperatures and pressure in the chamber31 in the respective steps of forming the above-described tunnel oxidefilm. The reference numerals in FIG. 8 respectively correspond to thestep numbers in FIG. 7.

[0066] In the E²PROM having the structure shown in FIG. 1F, writing anderasing of data are performed by supplying/extracting electrons in/fromthe floating gate 181 through the tunnel insulating film 14.

[0067] In a data writing operation of supplying electrons in thefloating gate 181, for example, a voltage of 18 to 25 V is applied tothe control gate 201, and the drain, the source, and the substrate 11are set at 0 V. In addition, in a data erasing operation of extractingelectrons from the floating gate 181, the control gate 201, the source,and the substrate 11 are set at 0 V, and a voltage of 18 to 25 V isapplied to the drain.

[0068] The tunnel oxide film formed in this manner has a structurerepresented by a band diagram shown in FIG. 9, wherein a surface of thetunnel oxide film and an interface side of the silicon substrate areformed into nitrided oxide films. Therefore, as indicated by brokenlines in FIG. 9, the barrier heights of tunnel portions at the surfaceof the tunnel oxide film and the interface portion are made lower thanthose of a tunnel oxide film consisting of only a silicon oxide (SiO₂)film.

[0069] As described above, the tunnel insulating film having athree-layer structure in which nitrided oxide films are formed on theupper and lower surfaces of a silicon oxide film can be formed in such amanner that the silicon oxide film formed in the seventh step, i.e.,step 107 is rapidly heated by the halogen lamps in an atmosphere of NH₃as in the 10th and 11th steps, i.e., steps 110 and 111.

[0070] The above-described nitriding means is described in, e.g.,Yasushi Naito et al., J, Vac. Technol, B5(3), May/Jun 1987, p. 633. Whenthe nitriding time is set to be short, nitrided oxide films are formedon the surface of a silicon oxide film and an interface. With the elapseof time, the entire oxide film becomes nitrided. This phenomenon wasconfirmed by an experiment performed by the present inventors.

[0071]FIG. 10 shows results obtained by the experiment. In this case, acurrent density J is set as “J=64 mA/cm²”, and a thickness Tox of atunnel oxide film is set to be 80 Å.

[0072] As is apparent from FIG. 10, a curve A represents a case whereina rapid nitriding time is set to be “0 seconds” and hence no rapidnitriding treatment is performed. In this case, a voltage Vg isincreased with the elapse of time. The voltage Vg corresponds to anamount of charge trapped in the tunnel oxide film.

[0073] In contrast to this, curves B and C respectively represent caseswherein rapid nitriding is performed at 1,150° C. for 10 seconds and atthe same temperature for 30 seconds. In these cases, the voltage Vgundergoes almost no change. However, as indicated by a curve D, if arapid nitriding treatment is performed for 100 seconds, the voltage Vgis rapidly increased.

[0074] If nitrided oxide films are formed on the upper and lowersurfaces of a silicon oxide film to form a three-layer structure, theresultant structure is kept in a state wherein a trap amount ofelectrons is small. In this case, since a drop in threshold voltage inthe endurance characteristics is small, even if the number of times ofwriting and erasing data is increased, stability thereof is maintained.

[0075]FIG. 11 shows endurance characteristics. Referring to FIG. 11, acurve A represents a case wherein a tunnel oxide film has a thickness of100 Å, and is rapidly nitrided at 1,150° C. for 30 seconds. In thiscase, a threshold voltage V_(T) exhibits almost no decrease uponrepetition of writing and erasing operations. In contrast to this, whenno nitride oxide layer is present, the threshold voltage V_(T) islowered and a V_(T) window is narrowed upon repetition of writing anderasing operations, as indicated by a curve B. Therefore, it is clearthat variations in threshold voltage V_(T) can be suppressed byperforming rapid nitriding.

[0076] By forming a three-layer structure wherein nitrided oxide layersare formed on the upper and lower surfaces of a tunnel oxide film inthis manner, endurance characteristics and breakdown characteristics canbe improved. As described in the 13th and 14th steps, i.e., steps 113and 114, since the heat treatment is performed after the rapid nitridingtreatment in the 21st step, the above characteristics can be furtherimproved.

[0077] After the rapid nitriding in the 11th step, i.e., step 111,nonreacted NH_(X), hydrogen, Hy₀ compounds, and the like are left in thetunnel oxide film. If these residues are contained in the film,breakdown time may be undesirably shortened due to electron trap. Asdescribed in the embodiment, however, by performing a heat treatment,the above-described nonreacted residues can be effectively eliminated,as shown in FIGS. 12A to 12C.

[0078]FIGS. 12A to 12C respectively show results obtained by measuringthe nitrogen concentration of each tunnel oxide film in its depthdirection by Auger analysis. FIG. 12A shows the characteristics of asample obtained by setting the nitriding temperature in the 11th step,i.e., step 111 to be 1,050° C. FIG. 12B shows the characteristics of asample obtained by setting the temperature at 1,150° C. FIG. 12C showsthe characteristics of a sample obtained by setting the temperature at1,250° C. In these drawings, broken curves are associated with sampleswithout a heat treatment, whereas solid curves represent thecharacteristics of samples subjected to the heat treatments.

[0079] Note that this experiment was performed such that a heattreatment was performed at 1,000° C. for 10 minutes by using an electricfurnace.

[0080] As is apparent from the results of this experiment, the nitrogenconcentration of each sample subjected to the heat treatment becomes lowcompared with the samples without a heat treatment. This tendencybecomes conspicuous with an increase in nitriding temperature. In thiscase, the hydrogen concentration of each film cannot be measured becausea hydrogen atom is too light. However, as is apparent from thecharacteristics shown in FIGS. 12A to 12C, since nitrogen is removed, itcan be determined that hydrogen atoms which are smaller than nitrogenatoms are more effectively removed.

[0081] Since nonreacted residues in a tunnel oxide film can beeliminated by a heat treatment in this manner, an electron trap amountcan be effectively reduced. Hence, excellent characteristics of theE²PROM can be obtained.

[0082] Note that nonreacted residues can be more satisfactorilyeliminated by the step of evacuation than by the step of introduction ofan inert gas in the 13th step, i.e., step 113, and hence the step ofevacuation is preferable.

[0083] As described above, a silicon oxide film is rapidly nitrided toform nitrided oxide layers on the upper and lower surfaces of the oxidefilm, thereby forming a tunnel oxide film having a three-layerstructure. In this case, the endurance characteristics and the breakdowncharacteristics can be improved. Such an improvement is considered to bebased on the following reasons.

[0084] If a tunnel oxide film portion is constituted by only a siliconoxide film, distorted strain bonds are present near the interfacebetween a silicon substrate and an SiO₂ film constituting the abovetunnel oxide film to cause so-called Si—O trapping. However, it isconsidered that if rapid nitriding is performed, and a certain amount ofnitrooxide is formed near the interface, distortion of the interface isreduced, and trapping is suppressed. In addition, the barrier height ofthis nitrided oxide film is smaller than that of the oxide film.Although the overall tunnel film is thick, its apparent thickness isconsidered to be small. It is considered, therefore, that trapping isfurther suppressed.

[0085] If, however, the entire oxide film was formed into a nitridedoxide film, it was found that the distortion was increased, the trapamount was considerably increased, and therefore, an optimal range waspresent.

[0086]FIG. 13 shows data based on an experiment, which represents arelationship between a nitriding (RTN) temperature y and a rapidnitriding (RTN) time t. In this experiment, a 4140B parameter analyzeravailable from Yokogawa Hewlett-Packard Co. was used to measure TDDBbreakdown time by applying a positive potential to a gate at a roomtemperature so as to cause a current to flow at the current density J=64mA/cm². Note that the tunnel oxide films of samples used in thisexperiment had thicknesses of 80 ±10 Å, and these tunnel oxide filmswere subjected to the heat treatments in the 13th and 14th steps, i.e.,steps 113 and 114.

[0087] Assume that an average breakdown time of samples having tunneloxide films which are not nitrided is set to be “1”. Referring to FIG.13, a line plot represents samples having breakdown time smaller than 1;single circle plots, samples having breakdown time larger than 1; doublecircle plots, samples having breakdown time larger than 2 (doublebreakdown time); and triple circle plots, samples having breakdown timelarger than 3.

[0088] As is apparent from this experiment, within the rangesubstantially satisfying the following relationship:

y≦−162 log t+1392

[0089] the breakdown time of a sample can be prolonged and itscharacteristics can be improved compared with a sample formed withoutnitriding a tunnel oxide film.

[0090]FIGS. 14A and 14B respectively show sectional structures of asemiconductor memory device according to another embodiment of thepresent invention. A step of forming a floating gate will be mainlydescribed with reference to these drawings. Other steps are known, andthe steps described in the first embodiment will be used as needed.

[0091] As shown in FIG. 14A, after a gate insulating film 40 and atunnel insulating film 41 are formed on a semiconductor substrate 11, apolysilicon film 42 which contains phosphorus at a low concentration ordoes not contain any impurity is formed. Oxygen and nitrogen ions arelocally implanted into the polysilicon film 42 so as to cover a regionabove the tunnel insulating film 41. The resultant structure is thensubjected to a heat treatment so that a barrier layer 43 for impuritydiffusion is formed in the polysilicon film 42.

[0092] Subsequently, as shown in FIG. 14B, phosphorus is diffused in thepolysilicon film 42 at a high concentration from a gaseous impuritysource of POCl₃ so as to form a region 421 near the tunnel insulatingfilm 41 into -a low-concentration impurity region.

[0093]FIG. 15 shows an embodiment wherein after a polysilicon film 45 isformed on a semiconductor substrate 11, an SiO₂ film or an Si₃N₄ film 46is formed above a tunnel insulating film 47.

[0094] Subsequently, a second polysilicon film 48 is formed on theresultant structure, and phosphorus is diffused in the same manner as inthe embodiment shown in FIGS. 14A and 14B.

[0095]FIG. 16 shows an embodiment wherein a gate insulating film 50 isformed on a semiconductor substrate 11, and a tunnel insulating film 51is locally formed in the film 50. Thereafter, a polysilicon film 52 isformed on the polysilicon film 51. A film 53 such as an SiO₂ or Si₃N₄film is locally formed on the polysilicon film 52 at a position abovethe tunnel insulating film 51. If phosphorus is then diffused at a highconcentration in the same manner as in the above-described embodiment, aregion 54 below the film 53 selectively has a low impurityconcentration.

[0096] According to this embodiment, a low-concentration region isformed in a flat portion on the polysilicon film 52, whereas an edgeportion has a high concentration. In addition, the manufacturing processcan be simplified, and hence this embodiment is advantageous in terms ofcost.

[0097]FIG. 17 shows an embodiment wherein a tunnel insulating film 56 islocally formed in a gate insulating film 55 formed on a semiconductorsubstrate 11. A first polysilicon film 57 having an impurity at a lowconcentration is formed on the gate insulating film 55. An oxide film 58having a thickness of 5 to 20 Å is formed on the first polysilicon film57. In this case, a natural oxide film or an oxide film formed when thestructure is boiled in a solution of H₂O₂—H₂SO₄ may be used. A secondpolysilicon film 59 having an impurity at a high concentration is formedon the oxide film 58. In this case, the impurity from the secondpolysilicon film 59 is not easily diffused into the first polysiliconfilm 57 because of the oxide film 58.

[0098] Note that since the thickness of the oxide film 58 issatisfactorily reduced, electrons can directly tunnel, and littleproblem is posed.

[0099]FIGS. 18A to 18D show manufacturing steps of a semiconductormemory device according to still another embodiment of the presentinvention. As shown in FIG. 18A, a tunnel insulating film 61 is locallyformed in a gate insulating film 60 formed on a semiconductor substrate11. A non-doped polysilicon film 62 is formed on this gate insulatingfilm 60. Thereafter, phosphorus is diffused from an impurity source ofPOCl₃ into the entire surface of the film 62 at 900 to 1,000° C, orphosphorus or arsenic is ion-implanted to set a low impurityconcentration.

[0100] As shown in FIG. 18B, an SiO₂ or Si₃N₄ film 63 having a thicknessof 500 to 1,000 Å0 is formed on the polysilicon film 62 by CVD orthermal oxidation. Subsequently, a resist film 64 is locally formed at aportion above a prospective floating region. As shown in FIG. 18C, thepolysilicon film 62 and the SiO₂ film 63 are selectively removed byusing the resist film 64 as a mask. Thereafter, an impurity is diffusedin the resultant structure at a high concentration at 900 to 1,000° C.by using POCl₃ or the like as an impurity source, thereby forming ahigh-concentration region 65. After the SiO₂ or Si₃N₄ film 63 is removedonce, an insulating interlayer 66 having a thickness of 400 to 1,000 Åis formed, as shown in FIG. 18D.

[0101] Note that gate oxide films of other elements such as MOS elementsare simultaneously formed at this time.

[0102] According to this embodiment, the endurance characteristics andthe breakdown characteristics of the tunnel insulating film can beimproved, and moreover, manufacturing steps of a normal E²PROM can beutilized without using a specific mask.

[0103]FIGS. 19A and 19B show an embodiment wherein the steps describedin the above embodiment with reference to FIGS. 18B and 18C aremodified, and other steps are the same as those thereof.

[0104] More specifically, as shown in FIG. 19A, a gate insulating film70 is formed on a surface of a semiconductor substrate 11, and a tunnelinsulating film 71 is locally formed in the film 70. In addition, apolysilicon film 72 is formed on the gate insulating film 70.Thereafter, an SiO₂ film 73 is formed on the polysilicon film 72. TheSiO₂ film 73 is wet-etched by a hydrofluoric acid etchant and using aresist film 74 as a mask or overetched by isotropic dry etching. Asshown in FIG. 19B, the polysilicon film 72 is then selectively removed.Thereafter, an impurity is introduced at a which concentration into thepolysilicon film 72 by using the SiO₂ film 73 as a mask, thus forming ahigh-concentration region 75.

[0105] In this embodiment, since the SiO₂ film is over-etched, theimpurity can be easily introduced into the polysilicon film 72.

[0106]FIG. 20 shows a sectional structure of a semiconductor memorydevice according to still another embodiment of the present invention. Adrain region 82 and a source region 83 are locally formed in P wellregion of a semiconductor substrate 81 consisting of silicon. A floatinggate 85 consisting of polysilicon is formed on a surface of thesemiconductor substrate 81 through an insulating layer 84 serving as atunnel oxide film. A control gate 87 consisting of polysilicon is formedon the floating gate 85 through an insulating layer 86. An insulatinglayer 88 is formed on the resultant structure so as to surround thefloating gate 85 and the control gate 87.

[0107] In this case, the insulating films 84, 86, and 88 are mainlyconstituted by oxide films 841, 861, and 881, respectively, each ofwhich consists of silicon oxide (SiO₂) obtained by a heat treatment inan oxygen atmosphere. Nitrided oxide layers 842, 862, and 882 arerespectively formed on the upper and lower surfaces of the silicon oxidefilms 841, 861, and 881. In this manner, these insulating layers 84, 86,and 88 are formed into three-layer structures.

[0108] A BPSG layer 90 is formed on the semiconductor substrate 81 so asto cover the floating gate 85 and the control gate 87. Aluminum wiringlayers 91 and 92 respectively extend from the drain region 82 and sourceregion 83 through the BPSG layer 90. Reference numeral 93 denotes aprotective passivation film.

[0109]FIGS. 21A to 21J sequentially show manufacturing steps of asemiconductor memory device such as described above, more specifically,a memory cell portion of an EPROM. As shown in FIG. 21A, a field oxidefilm region is formed in a P well formation region of a semiconductorsubstrate 81 consisting of silicon by a LOCOS method. An oxide film 131consisting of SiO₂ and having a thickness of 200 to 500 Å0 is formed onthe substrate 81. A silicon nitride (Si₃N₄) layer 132 having a thicknessof 1,000 to 2,000 Å is formed on the oxide film 131 and is then formedinto a pattern shape by photolithography or etching. Boron ions areimplanted into the substrate 81 by using the silicon nitride layer 132as a mask to form a p⁺-channel stopper region 133. Thereafter, a fieldoxide film 134 having a thickness of 0.5 to 1.5 μm is formed in steam of1,000° C., as shown in FIG. 21B.

[0110] The oxide film 131 and the silicon nitride layer 132 are removedin this state. Thereafter, a gate 135 consisting of a silicon oxide filmhaving a thickness of 200 to 500 Å0 is formed, as shown in FIG. 21C.

[0111] When the gate oxide film 135 is formed in this manner, thesemiconductor substrate 81 is set in an atmosphere of a nitrogen gas andrapidly heated to form nitrided oxide layers 351 and 352 respectively onthe upper and lower surfaces of the gate oxide film 135, as shown inFIG. 21D. These nitrided oxide layers are formed in the same manner asin the method described with reference to FIG. 7.

[0112] When the gate oxide film 135 having a three-layer structure isformed in this manner, a first n⁺-type polysilicon layer 136 having athickness of 3,000 to 5,000 Å is formed on the resultant structure. Inaddition, an oxide film layer 137 is formed on the polysilicon layer 136by thermal oxidation, as shown in FIG. 21F. This oxide film layer 137 issubjected to a rapid nitriding treatment as in the case of the gateoxide film 135 to form nitrided oxide layers 371 and 372 on the upperand lower surfaces of the oxide film layer 137, as shown in FIG. 21G.

[0113] When the oxide film layer 137 having the nitrided oxide layers onits upper and lower surfaces is formed in this manner, a secondpolysilicon layer 138 having a thickness of 3,000 to 5,000 Å is formedon the layer 137, as shown in FIG. 21H. In this state, parts of thesecond polysilicon layer 138, the oxide film layer 137, and the firstpolysilicon layer 136 are removed by etching. As a result, a floatinggate and a control gate of, e.g., an EPROM are constituted by the firstand second polysilicon layers 136 and 138 upon partial removal thereof.

[0114] Subsequently, as shown in FIG. 21I, a thermal oxide film 139 isformed on peripheral portions of the gates. Nitrided oxide layers 391and 392 are then formed on the upper and lower surfaces of the thermaloxide film 139 by a rapid nitriding treatment in the same manner asdescribed above, as shown in FIG. 21J. A source, a drain, a BPSGinsulating interlayer, and aluminum wiring layers are formed on theresultant structure, thereby completing the semiconductor memory deviceshown in FIG. 20.

[0115] Although the impurity concentration of the first polysiliconlayer 136 serving as a floating gate is not specifically described inthe above manufacturing steps, it is set to be lower than that of thesecond polysilicon layer 138.

What is claimed is:
 1. A semiconductor memory device comprising: asemiconductor substrate; a gate insulating film formed on a surface ofsaid semiconductor substrate; a tunnel insulating film obtained byforming a portion of said gate insulating film into a thin layer; and afloating gate formed on said gate insulating film, a portion of saidfloating gate corresponding to said tunnel insulating film having animpurity concentration lower than that of other portions.
 2. Anapparatus according to claim 1, wherein a first conductive layer havinga low impurity concentration is formed on a tunnel region portion ofsaid semiconductor substrate through said tunnel insulating film, and asecond conductive layer having an impurity concentration higher thanthat of said first conductive layer is formed on said first conductivelayer so as to be electrically connected thereto, said first and secondconductive layers constituting said floating gate.
 3. An apparatusaccording to claim 1, wherein a barrier layer against impurity diffusionis formed above said tunnel insulating film of said floating gate, andan impurity concentration of a portion of said floating gate betweensaid barrier layer and said tunnel insulating film is set to be lowerthan that of other portions of said floating gate.
 4. An apparatusaccording to claim 1, wherein said other portions with respect to saidportion corresponding to said tunnel insulating film include portions incontact with an oxide film formed on a surface of said floating gate. 5.A method of manufacturing a semiconductor memory device, comprising: afirst step of forming a first insulating film at a positioncorresponding to a tunnel region on a surface of a semiconductorsubstrate, and forming a second insulating film having a thicknesslarger than that of said first insulating film on portions other thansaid tunnel region so as to be in contact with said first insulatingfilm; a second step of forming a floating gate on said gate insulatingfilm including a portion on said tunnel region, and setting an impurityconcentration of at least a portion of said floating gate correspondingto said tunnel region to be lower than that of other portions; and athird step of forming a control gate on said floating gate through athird insulating film.
 6. A method according to claim 5, wherein thesecond step of forming said floating gate includes the steps of forminga first conductive film having a low impurity concentration so as to bein contact with said first insulating film, etching said firstconductive film in accordance with a predetermined pattern to form saidportion in contact with said first insulating film, and forming a secondconductive film having an impurity concentration higher than that ofsaid first conductive layer so as to be in contact therewith, therebyforming said other portions.
 7. A method according to claim 5, whereinthe first step of forming said first insulating film includes the stepsof oxidizing a surface of said semiconductor substrate to form an oxidefilm, and nitriding said oxide film to form a nitrided oxide film.
 8. Amethod according to claim 5, wherein the second step comprises the stepof forming a first conductive layer of a low impurity concentration in amanner to correspond to the first insulation film portion, and the stepof forming a second conductive layer on the first conductive layer, saidsecond conductive layer having an impurity concentration higher thanthat in the first conductive layer.
 9. A method according to claim 5,wherein the first step includes the steps of forming a thermal oxidefilm on said semiconductor substrate, and performing a nitridingtreatment in an atmosphere containing a nitrogen gas by rapid heating toform said thermal oxide film into a three-layer structure constituted bya nitrided oxide film and an oxide film.
 10. A method according to claim5, wherein said second step includes a step of forming a conductivelayer serving as a floating gate on said first and second insulatingfilms, a step of forming a barrier layer in said conductive layer at aposition corresponding to said tunnel region, and a step of diffusing animpurity into said conductive layer to set an impurity concentration ofa portion of said conductive layer corresponding to said tunnel regionbetween said first insulating film and said barrier layer to be lowerthan that of other portions.
 11. A method according to claim 10, whereinthe barrier layer-forming step includes implanting ions into saidportion of said conductive layer corresponding to said tunnel region andperforming a heat treatment to form a barrier layer against impuritydiffusion.
 12. A method according to claim 10, wherein the conductivelayer-forming and barrier layer-forming steps include the steps offorming a first conductive layer on said first and second insulatinglayers, forming an insulating film on a portion of said first insulatingfilm corresponding to said tunnel region, and forming a secondconductive layer on said insulating film, said floating gate beingconstituted by said first and second conductive layers, and said barrierlayer being constituted by said insulating film.
 13. A method accordingto claim 10, wherein the barrier layer-forming step comprises forming aninsulating film on said conductive layer formed in the second step at aposition corresponding to said tunnel region.
 14. A method according toclaim 5, wherein said second step includes a step of forming aconductive layer serving as a floating region on said second insulatinglayer including a portion on said first insulating layer, a step offorming an insulating layer on said conductive layer by thermaloxidation, and a step of diffusing an impurity into said conductivelayer to form a high-concentration region in a portion of saidconductive layer surrounding said tunnel region.
 15. A method ofmanufacturing a tunnel insulating layer of a semiconductor memorydevice, comprising: a first step of evacuating a chamber in which asemiconductor substrate is set; a second step of introducing a reactivegas into said evacuated chamber, and raising a temperature of saidchamber to remove a natural oxide film formed on a surface of saidsemiconductor substrate; a third step of evacuating said chamber andintroducing oxygen therein; a fourth step of rapidly oxidizing thesurface of said semiconductor substrate in said chamber in which theoxygen is introduced to form an oxide film; a fifth step of evacuatingsaid chamber and introducing a nitrogen reactive gas therein; and asixth step of rapidly heating the surface of said semiconductorsubstrate set in said chamber in which the nitrogen reactive gas isintroduced to form nitrided oxide layers on upper and lower surfaces ofsaid oxide film.
 16. A method according to claim 15, wherein a halogenlamp or an arc lamp is used as a heating source in the sixth step.
 17. Amethod of manufacturing a semiconductor memory device, comprising: afirst step of forming an oxide film on a surface of a semiconductorsubstrate; a second step of setting the substrate having the oxide filmformed thereon within a chamber into which a nitrogen-containingreaction gas is introduced and rapidly heating the substrate to form anoxynitride film by the nitriding reaction on the surface of the oxidefilm formed on the semiconductor substrate; and a third step ofevacuating the chamber and heating the substrate under a reducedpressure so as to remove the unreacted residue within the oxide film andthe oxynitride film.
 18. A method according to claim 17, wherein thenitriding time t and the nitriding temperature y in the second step areset to meet the relationship of: y≦−162 log t+1392.